The exemplary embodiments of this invention relate generally to semiconductor devices and techniques for the fabrication thereof and, more specifically, to structures and methods for the efficient flow of heat through semiconductor devices.
A complementary metal oxide semiconductor device (CMOS) uses pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on silicon or silicon-on-insulator (SOI) substrates. A MOSFET, which is used for amplifying or switching electronic signals for logic functions, has source and drain regions connected by a channel. The source region is a terminal through which current enters the channel, and the drain region is a terminal through which current leaves the channel. A gate overlies the channel and controls the flow of current between the source and drain regions. In some devices, the channel may be a thin “fin” through which the gate controls the flow of current, thereby making the PFETs and NFETs “finFET” devices. In other devices, the channel may be a nanowire, thereby defining the devices as nanowire-FET devices.
There is a continued desire to reduce the size of structural features of such devices in order to provide a greater amount of circuitry on a given integrated circuit (IC) chip. Doing so generally allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. However, the present technology is at or approaching atomic level scaling of certain micro-devices.
With continued device scaling (higher power densities, etc.), local heating in IC chips is reaching levels that could impact system reliability. Particularly with regard to finFETs and nanowire-FET geometries, the effects of device heating have become worse as compared to planar technologies. In addition to heating problems at the circuit scale (about 100-1000 micrometers), individual devices themselves may heat up and create micro-hot-spots on an IC chip. Excess heating of devices or excess heat on an IC chip may cause an unnecessary dissipation of power, thereby compromising device or circuit efficiency and reliability. For example, heat may cause power to be dissipated in an SOI layer located between a buried oxide (BOX) layer and a dielectric layer.
Presently, heat sinking is often carried out at a package level. In other words, heat is removed from circuits and devices in bulk via thermal transport from a device region to a heat sink through passive transport mechanisms such as thermal conduction.
Heat may also be removed from some circuits using Peltier cooling. Peltier cooling may be achieved through the use of additional structures by incorporating Peltier junctions that are separate from the actual device from which heat is desired to be removed. This type of cooling, however, suffers from a few main drawbacks, namely, (1) Peltier junctions are not intrinsically integrated into the devices themselves, which reduces cooling efficiency; (2) Peltier cooling requires additional power supply into the system; and (3) in addition to fabrication of the actual semiconductor device, Peltier cooling structures need also to be fabricated, thus increasing process/integration complexity.